Hardware Experience:

Involved in Product development of hardware accelerated 3D algorithms. Developed hardware accelerated algorithms to do registration, volume rendering, and fusion of 3D medical data using high performance hardware boards.

DSP/Native acceleration of medical applications:
Involved in developing an accelerated 3D Angiography software package on several target platforms. They included: multiple Pentium PC (Multithreaded), a parallel DSP board, the TMS320C6201 DSP, and an Alpha based machine.

Micro-controller/DSP based digital camera library:
Involved in developing a high performance, embedded image-processing library for a digital camera based on the TriCore DSP/Micro-controller. The tasks included designing and coding the camera library, optimizing the algorithms for the TriCore processor (assembler level coding), and contributing to the overall camera hardware system definition. Used tolls like C, Tricore IDE, and Windows NT. The library was delivered for release as part of a camera reference design product.

Accelerated video algorithms:
Involved in developing an accelerated video-processing library for video surveillance applications. The library was developed using Intel MMX and streaming SIMD instructions. Components of the library were used to develop applications in Video based monitoring, tracking and matching for industrial applications. Utilized PC, NT and Visual C++.

Parallel DSP based algorithm development for medical applications:
Involved in developing a parallel image-balancing algorithm for artifact removal in Computed Tomography (CT) images using a SHARC based DSP board. The tasks included: development of a parallel algorithm and implementing it on a parallel DSP SHARC board from Mercury Computers. Utilized skills like C, Mercury Computers parallel IDE (real-time OS, SHARC assembler level coding). The algorithm was delivered for integration within the CT reconstruction product line.

DSP based architecture development/simulation:
Worked on a scalable architecture for Ultrasound applications project. A parallel architecture for ultrasound processing was developed using commercial off the shelf DSP processors (TMS320C40, and ADI 21060) to replace an existing dedicated hardware implementation. This involved developing the architecture, mapping 20+ 1D and 2D algorithms (including those dealing with RF signals) to the architecture, doing high level hardware design, and then simulating the algorithms running on the architecture to validate the approach. A real-time parallel scheduling algorithm for DSP applications (ultrasound) was also developed. The results were incorporated in a next generation Ultrasound machine. Tools used included C/C++, high level simulation tools (Verilog-XL, Leapfrog-VHDL, SES/Workbench) and models from Logic Modeling Inc. The assembler/compiler for TI & ADI DSPs were also used.

DSP based Fourier reconstruction engine:
Involved in parallel DSP based architecture using the Analog Devices SHARC processor to do computed tomography using a Fourier based approach. Developed a parallel version of the approach, mapped it to SHARC DSP array based architecture and performed high level simulation to validate the approach. The approach was transferred for use in a product line. Worked with C/C++, SES/Workbench high-level simulation tool, and the SHARC assembler/compiler.

Algorithm mapping to target architectures:
Involved in creating a scalable architecture for 1D/2D signal processing applications project. A core of computationally intensive algorithms was identified and an SIMD type architecture using TI's TMS320C40 was developed to speed-up select computationally intensive signal processing applications. A hardware design was then developed. The core algorithms were then mapped to the architecture and simulation runs were performed to evaluate the scalability and performance/cost tradeoffs of several medical applications using the architecture. The results from this project were transferred for use in medical applications. Tools used were C/C++, SES/Workbench, TMS320C40 assembler/compiler and Cadence CAD.

FPGA based hardware development:
Involved in a reconfigurable hardware project. An FPGA implementation for a morphology accelerator was developed. The accelerator uses a systolic architecture, a 14x13 structuring element, Xilinx FPGAs and interfaces to a Data cube machine. Used Cadence design tools including Verilog-XL/VHDL Leapfrog simulators, Logic/component libraries, place and route tools, and Hspice. The SES/Workbench simulator was also used.

VLSI CAD Tool Developer, CAD Tools development :
Involved in developing an artificial intelligence based knowledge acquisition tool for use in a high-level design assistant for VLSI Design tool. The tool was written in the expert system shell ART.